A power-on reset (POR) circuit provides a reset signal for a subsystem, or subsystems, in a computer system. More specifically, a power-on reset output signal POR*, usually an active low signal, of the POR circuit is asserted low for a period of time when the power provided to the computer system is initially switched on. FIGS. 1A and 1B illustrate typical timing diagrams of power provided to a computer system and the signal POR*. The power provided to the computer system, for example V.sub.dd, is represented by waveform 10 in FIG. 1A and switches on in a time period equal to (t.sub.2 -t.sub.1). The power-on reset output signal POR*, represented by waveform 12 in FIG. 1B, is necessarily asserted low in this same time period (t.sub.2 -t.sub.1). Further, the signal POR* is usually maintained in the active low state for another time period equal to (t.sub.3 -t.sub.2). In this time period (t.sub.3 -t.sub.2), a controller, such as a central processing unit (CPU), initiates its internal status, and some peripheral chips, such as a direct memory access (DMA) controller or a universal asynchronous receiver/transmitter (UART), clear their registers. A typical active time period, (t.sub.3 -t.sub.1) of the signal POR* is in the range of about 10 ms to 100 ms. This time period (t.sub.3 -t.sub.1) is long compared with the switching time of a metal oxide semiconductor (MOS) transistor (usually 0.0005 ms for a 0.5 .mu.m process).
Power-on reset (POR) circuits known in the art are implemented either inside or outside a chip, depending on the particular application. For example, a conventional POR circuit for a CPU chip is built outside the CPU chip, while a POR circuit for a peripheral chip may be built either inside or outside the chip.
A conventional POR circuit includes an RC network to generate the signal POR*. For example, an RC circuit with a resistor having a value of about 1 Mohm and a capacitor having a value of about 0.1 .mu.F will generate the signal POR* having an active time of about 82 ms. FIG. 2 shows a schematic diagram illustrating a typical POR circuit with an RC circuit fabricated in an integrated circuit. In the circuit of FIG. 2, a capacitor 20 is implemented with a p-type metal oxide semiconductor (PMOS) transistor having its source, drain, and substrate (or body) connected to ground. The capacitance of the capacitor 20 is determined by the size of the PMOS transistor used. More specifically, a PMOS transistor occupying more area results in a capacitor having more parasitic capacitance, that dominates the total capacitance. Moreover, the parasitic capacitance of a PMOS transistor is about three times the parasitic capacitance of an n-type metal oxide semiconductor (NMOS) transistor having the same size as the PMOS transistor. Therefore, the PMOS transistor is conventionally used as a capacitor instead of the NMOS transistor.
Still referring to FIG. 2, a resistor 22 is implemented with another PMOS transistor having its source and substrate connected to a supply line for voltage V.sub.dd, and its gate connected to ground. The PMOS transistor 22 also has its drain connected to the gate of the PMOS transistor connected as the capacitor 20. Because a PMOS transistor has a larger parasitic sheet resistance in its channel than an NMOS transistor, the resistor of an RC circuit is usually implemented by a PMOS transistor. The output signal from the drain of the PMOS transistor connected as the resistor 22 is usually connected to an input line of cascaded inverters 24, that commonly include two NOT gates 240 and 242 connected in series. The cascaded inverters 24 are used to shape the signal connected to its input line to a better form, and the required signal POR* is then provided at the output line of the cascaded inverters 24.
The POR circuit of FIG. 2 can be fabricated with a peripheral circuit (not shown in this figure) in the same chip to reduce the total count of components on a system board. However, the area occupied by the resistor 22 and the capacitor 20 is very large compared with standard devices such as logic gates or flip-flops. For example, the typical parasitic capacitance of a PMOS transistor is 0.4 pF/.mu.m.sup.2. Consequently, an area of about 250,000 .mu.m.sub.2 is required to fabricate a capacitor having a capacitance of 0.1 .mu.F. This occupied area is about the total area of 2200 two-input NAND gates for a 0.5 .mu.m process. Further, the typical sheet resistance of the PMOS transistor is 2.5.times.10.sup.4 ohms per square. Consequently, an area of about 80 .mu.m.sub.2 is required to fabricate a resistor having a resistance of 1 Mohm. Unfortunately, the area used for fabricating the capacitor will not shrink while the technology of the semiconductor industry progresses. Therefore, the area occupied by the PMOS capacitor becomes a dominant factor in determining the chip size.